VLSI SKILL SET

 A SURVEY ON VLSI SKILL SET

(survey done till 11th dec,2020 11.59PM)

QUESTIONS AND RESPONSES OF SURVEY:

        From the above survey the following points be concluded that,

        The for doing career in VLSI industry we must be perfect in the core subject of Elecctronic Engg.

and we must be have good command on programming skills like verilog and must have experience of doing / working project on VLSI inndustry as intern or apprentship.

As from survey one more point is clear that there is scope of VLSI Test Engg.

The following is the way of VLSI Design is as follows:

VLSI  Design:

        A .Chip Devloping Process

        B.VLSI Cicuit Design Processor

        C. Design Flow

        D. Design Styles

Introduction:

    VLSI design is a sequential process of generating the physical layout of an IC, starting from the specification of that circuit it can be fully or semi-automated using numerous software called electronic design automation(EDA) or computer aided design (CAD) tools. The designer first get an idea of a new system or a device for a particular application. This new idea is translated in the form of an integrated circuit chip using the VLSI design flow.

Chip Developing Process:

    The Process of devloping a chip from concept to silicon is divided into the following four tasks: design, verification, implementation and software .

a) Design:

    often starts with marketing research and product defination and is followed by system design.It ends with RTL coding.

b)Verification:

    is a means of ensuring that the chip can perform faithfully in functionality , according to its design specifications. It includes verification at the system .RTL , and gate levels , and sometimes even at the transistor level. This bug -finding struggle continues until the chip is ready for production.

C) Implementation:

    is the process of actually creating the hardware , which results in an entity that one can see and feel .It includes both the logical and Physical implementations.

d)Software Devlopment:

    is the process of programming the brain of the chip (the on chip processors), or arming the chip with intelligence.

VLSI Circuit Design Process:

    Design Process:

    An interactive process that refines an IDEA to a manufacturable device (chip) through at least five levels of design abstraction.

Abstraction:

Hierarchical decomposition or "divide and conquer" is a useful methodology that partitions the entire system into its components. The components are again partitioned into modules and this process continues until the basic building blocks are reached. Thus very effective means of dealing with design complexity creating a model at a higher level of abstraction involves replacing details at low levels with simplifications. A system behaviour should be understood from this top level(chip as a whole) to the simple transistor level in the ic design process.

Design  flow:

A design flow is a sequence  of operations that transforms the IC designers intension{ usually represented in RTl  format} into layout. The design flow for a typical IC project is shown in figure{2.4}.

 

CONCEPT AND MARKET RESEARCH:

A detailed research about the tools available for designing the IC according to the  speacification  given in the requirements documents done thoroughly.

 

Architecture specification and design constrains:

The design idea refined into a set of requirements is known as specification. The general specification are,

1.What does the chip do?

2.How fast it need to operate in order to be compititive in market?

3.How much power will it consume?

4.How big will it be?

 

HDL CAPTURE AND RTL COADING

The design of integrated allows the circuit{ICs} in an art. During a half century of IC development, it has gradually become clear that there is a need for a computer language to describre  the structure and function of integrated circuits, or for describing on entire electronic system. As a result, two HDL languages, Verilog and VHDL, have been standardized and have emerged as the tools for IC design.

An HDL is created to meet a number of needs in the design process:

1:HDL allows the description of structure of a hardware system.

2.HDL can be used to described how the system is decomposed in to building blocks and how those building blocks are interconnected.

3. It allows the specification of system functionally by using the form of familiar programming languages.

4.The design of a system can be simulated before being manufactured so that designers can quickly compare alternatives and test for corrections without the delay and expense of hardware prototyping.

5.It allows the detailed structure of he design to be synthesized from a more abstract specification, allowing the designers to concentrate more on strategic design decisions. This automatic synthesis process also helps reduce design implantation time.

 

LOGIC SIMULATION:

Simulation is the use of a computer programe to simulate the operation of a digital circuit. logic stimulation is the primary tool used for verifying the logical correctness of a hardware design. In many logic simulation is the first activity performed in the process of taking a hardware design from concept to realization . modern hardware description are both simulatable and synthesizable.

 

LOGIC SYNTHESIS:

Logic synthesis is the process of translating an abstract form of desired circuit behaviour { typically in RTL} into design implementation in terms of logic gates.

 

LOGIC OPTIMIZATION:

Logic optimization a part of logic synthesis, is the process of finding an equivalent representation of the specified logic circuit under one or more specified constraints. Generally, the circuit is constrained to minimum chip area meeting a prespesified  delay. with the advent of net list reprentation of the given design description. Today , logic optimization is devided in to various categories based on two criteria:

BASED ON CIRCIUT REPRESNTATION :

1.Two -level logic optimization

2.Multi-level logic optimization.

BASED ON CIRCUIT CHARACTERISTICS:

1.Sequential logic optimization.

2.Combinational logic optimization.

FORMAL VERIFICATION:

Reification is the process of cheaking the designs functional correctness. This process can consume over 60% of the total design resoures in todays large , complicated chip designs.

Formal verifications techniques perform validation of a design using mathematical methods without the need for technological considerations, such as timing and physical effects. they chaeck for logical functions of a designed by comparing it against the reference design.

The perpose of the formal verification in the design flow is to validate the RTL against RTL ,gate-level netlist against the RTL code, or the comparison between gate-level netlists. The RTL to RTL verification is used to validate the  new RTL against the old functionally correct RTL . this is usually performed fpr designed that are subject to frequent changes in order to accommodate additional features. When these features are added to the sourse RTL ,here is always a risk of breaking the old  functionally correct  features .To prevent this, formal verification may be perform between the old RTL and the new RTL to check the validity of the old functionality.

STATIC TIMING ANALYSIS:

Static timing analysis {STA} is a method of computing the expected timing of signals inside a digital circuit without using stimulation.

STA is not designed for verifying the designs functional correctness but to cheak its timing validity .it locates the worst  case delay of the circuit over all possible input combinations. There are huge numbers of logic path inside a chip of complex design. The advantages of STA is that itperforms timimg analysis on all possible paths. In other words , unlike simulation, which only cheak timing on given paths, STAis a complete timing cheak all that cover of the paths, wheather they are real or potential false paths

 

 

 Author name:

Rohan Awale 

 Ref:

NPTEL Lec of Digital Design